This invention relates, in general, to buffer circuits, and more particularly, to mixed power supply tri-state buffer circuits.
A bus system is well known by one skilled in the art for interconnecting multiple integrated circuits together. Tri-state buffer circuits are commonly incorporated at the outputs of each integrated circuit for reading and writing to a bus. In general, integrated circuits coupled to a bus system operate at the same voltage and provide signals having similar voltage magnitudes. For example, the standard for operating CMOS (complementary metal oxide semiconductor) digital logic circuits has been five volts. A one logic level corresponds to a signal of approximately five volts while a zero logic level corresponds to a signal having ground potential. The supply voltage for CMOS digital logic circuits is migrating from five volts to three volts due to integrated circuit processing advances. Higher density integrated circuit processes utilize smaller geometry transistors and more levels of interconnect to increase circuit density. The transistors must be biased at three volts or less due to the smaller geometry to prevent damage.
Mixed mode operation occurs when circuits operating at three volts and five volts are coupled together. A simple example is described by coupling three and five volt digital logic circuits to a common bus. Both circuit types can read and write data to the bus but the magnitudes of the logic one levels of each will differ depending on the operating voltage. A problem with mixed mode operation is that the three volt tri-state buffers may not be able to withstand a five volt signal without damaging itself or producing large leakage currents.
A standard tri-state buffer design (for non-mixed mode operation) suffers from a high current drain problem at the drain of the p-channel output device when the bus voltage exceeds its supply voltage. The bulk (n-type region) of the p-channel output device couples to the supply voltage of the tri-state buffer (for example 3 volts). The drain (p-type) of the p-channel output device couples to the bus. The PN diode formed by the bulk and drain becomes forward biased when the voltage on the bus reaches a diode drop above its supply voltage.
Buffer circuits have been designed that can interface and receive five volt signals for mixed mode applications. An example of such a circuit is described in U.S. Pat. No. 5,151,619, by John S. Austin et al. entitled "CMOS OFF CHIP DRIVER CIRCUIT" the material of which is incorporated by reference herein.
A problem may occur when buffer circuits are tri-stated and coupled to a floating bus. The voltage on a floating bus can vary from the minimum to the maximum bus voltage due to leakage currents from the integrated circuits coupled thereto. This is a problem in that a buffer circuit could latch up or have leakage currents that exceed specification at a particular voltage on the bus.
Hence, it would be of great benefit if a mixed mode buffer circuit could be provided that does not leak over any portion of the entire operating voltage range and is not prone to latch up.